It is known to provide data processing systems incorporating memories with self-testing mechanisms, sometimes termed built-in self-test (BIST), such that when the memory circuits have been fabricated they may conduct a self-test or series of self-tests to determine if there are any memory defects present that would indicate that the circuit should be rejected. It is important that memory circuits should be highly reliable and that defective circuits should be effectively identified. As memory sizes increase, the proportion of the die being taken up by the memory is also increasing and, furthermore, the high transistor density within memory means that the defect density of these memories is becoming increasingly significant.
A known technique which alleviates such problems is to provide the integrated circuit with a memory Built In Self-Test (BIST) controller. In simplistic terms, a memory BIST controller is an on-chip utility that enables the execution of a proven set of algorithmic style verification tests directly on the embedded memory. These tests involve sequences of reads and writes to different addresses in the memory. Seed data defined by the BIST controller is written to and read from each memory address. Each read is compared against the expected read data. These tests can be executed at the design's full operating frequency to prove the memory operations and identify errors caused by silicon defects.
Memory BIST can be used both at the time of fabrication and when the chip is deployed in the field and performing its designed function. In the latter circumstance the memory BIST is activated at regular intervals (say once a second) to ensure that no errors have occurred in the memory. An ABS system, for example, will regularly self-check the behaviour of the chip including the memories. This can be done using self-checking code or by using memory BIST. Processors connected to the memory under test will not be able to access the memory during the test and will therefore stop execution. It is therefore important that the test be performed quickly and efficiently so that the time that the processor is stopped for is minimised. It is also important that in the absence of faults the memory content immediately before and after the test is identical.
Transparent memory BIST algorithms have been developed to address this problem, they perform their tests using the data stored in the memory as seed data. This avoids the need to save and restore the data to another memory at the beginning and end of the test. Hence the tests can be performed more quickly. However, although these tests may be performed more quickly, the processor will still not be able to handle any interrupts received during the test but will have to wait until it is completed. This is a serious concern in real time systems where interrupt latency is a key requirement.
In this respect, a typical transparent BIST algorithm will access each address 15 times during the test, this is known as 15N. This gives a maximum interrupt latency of 15X (number of RAM addresses), and an average interrupt latency of half this.
A more complex algorithm such as 22N will have a proportionately longer maximum and average interrupt latency. It should be noted that for a cache data RAM, 512 is a typical value for N.
A transparent circular algorithm for testing both on and off-line embedded memories which provides for restoration of the content at the end is disclosed in Karpovsky and Yarmolik “Transparent Memory BIST”, Proc IEEE int Workshop Memory Tech Des. Test, pp 106-111, 1994.
A known system involving the storing and restoring of state which is generally used in power down mode but can be used in memory BIST is disclosed in patent application GB02265023.